The current trend in the development of integrated semiconductor memories is aimed at increasingly miniaturizing the memory products and thus reducing internal and external voltages. At the same time, memory products are intended to be designed for an ever larger temperature range, such as use in mobile systems. This leads to ever more stringent requirements in ensuring the functionality of memory products in the specified temperature range. Attempts are currently being made to cover a wide temperature range through optimized design techniques and improved technological methods. In terms of design, voltage regulators are provided, for example, which generate voltages in temperature-independent fashion, in part derived from so-called bandgap circuits. In the case of the methods for fabricating integrated semiconductor memories, use is made of implantation techniques that are intended to ensure the functionality of memory products in an extended temperature range. Optimization of fabrication and design techniques is made more difficult by the fact that different and in part opposing requirements are made of the integrated semiconductor memory in order to ensure the functionality at high and low temperatures.
To illustrate the physical effects that occur at high and low temperatures, a DRAM memory cell is represented in FIG. 1. The memory cell SZ comprises a selection transistor AT and a storage capacitor SC. The first electrode of the storage capacitor SC is connected to a terminal M for applying a reference potential Vplate. The second electrode of the storage capacitor SC is connected to a bit line BL via a controllable path of the selection transistor. A control terminal ST of the selection transistor is connected to a word line WL. A substrate terminal of the selection transistor is connected to a potential Vbb.
If the memory cell is intended to be accessed, then a potential VPP that switches the selection transistor AT into the on state is generated on the word line. In this case, the storage capacitor is connected to the bit line via the turned-on path of the selection transistor. During a read access, the storage capacitor SC is discharged and alters the potential of the bit line. If a charge corresponding to the logic state 0 (low state) is present on the storage capacitor, then the bit line assumes the potential Vbll. If a charge corresponding to the logic state 1 (high state) is present on the storage capacitor, then the bit line assumes the potential Vblh. If an information item corresponding to the low state is intended to be stored in the memory cell during a write access, then the potential Vbll is generated on the bit line. If an information item corresponding to the high state is intended to be stored in the memory cell, then the potential Vblh is generated on the bit line and correspondingly charges the storage capacitor SC. When the memory cell is not active, the selection transistor is operated in the off-state mode, so that the storage capacitor is not conductively connected to the bit line. The potential VNWLL is generated on the word line WL in this case.
If the integrated semiconductor memory is operated at low temperatures, then the threshold voltage of the selection transistor increases. At the same time, the resistance also increases and thus so does the RC constant for writing an information item to the memory cell. In this case, the increase in the threshold voltage results from the increase in the Fermi voltage and the decrease in the intrinsic charge carrier density at low temperatures. Both effects ensure that, for example, when writing a 1 information item, a lower charge is stored in the storage capacitor SC than is the case at high temperatures.
If the integrated semiconductor memory is operated at higher temperatures, then the threshold voltage decreases. At the same time, the so-called subthreshold swing also increases. The subthreshold swing is a characteristic figure that describes the subthreshold behavior and thus the closing behavior of the selection transistor AT. At high temperatures, increased leakage currents occur when the selection transistor is operated in the off-state region. The consequence is that the charge stored in the storage capacitor SC flows away, which may lead to an information loss of the information stored in the memory cell SZ.
The requirements made of the magnitude of a suitable control voltage of the selection transistor during operation of the memory cell SZ in different temperature ranges are thus opposing. In the low-temperature range, an increase in the control voltage is desirable since the threshold voltage of the selection transistor also increases. In the high-temperature range, by contrast, an increase in the control voltage leads to an increase in the leakage currents, so that the use of a lower control voltage is recommendable in this case. The use of a single control voltage for the operation of the integrated semiconductor memory in the high- and low-temperature ranges therefore requires a compromise in the choice of the control voltages of the selection transistors. As a consequence there are power and quality losses during operation in high- and low-temperature ranges.